1. Field of the Invention
This invention relates generally to a method and device for controlling the transmission of information by a station to and from an ethernet and, more particularly, to a method and device for increasing the performance of the transmission of information and even more particularly, to a data structure to support multiple tranmsit packets for high performance.
2. Discussion of the Related Art
This invention is related to U.S. patent application Ser. No. 08/659,795 now U.S. Pat. No. 5,819,113 entitled "END OF PACKET DETECTION FOR STORING MULTIPLE PACKETS IN AN SRAM" invented by Alok Singh and Rajat Roy and U.S. patent application Ser. No. 08/669,728 now U.S. Pat. No. 5,818,844, entitled "ADDRESS GENERATION AND DATA PATH ARBITRATION TO AND FROM SRAM TO ACCOMMODATE MULTIPLE TRANSMITTED PACKETS" invented by Alok Singh, Rajat Roy, and Jerry Kuo, both applications assigned to the assignee of this application and both filed on the same date as this application.
A local-area network ("LAN") is a communication system that enables personal computers, work stations, file servers, repeaters, data terminal equipment ("DTE"), and other such information processing equipment located within a limited geographical area such as an office, a building, or a cluster of buildings to electronically transfer information among one another. Each piece of information processing equipment in the LAN communicates with other information processing equipment in the LAN by following a fixed protocol (or standard) which defines the network operation.
The ISO Open Systems Interconnection Basic Reference Model defines a seven-layer model for data communications in a LAN. The lowest layer in the model is the physical layer which consists of modules that specify (a) the physical media which interconnects the network nodes and over which data is to be electronically transmitted, (b) the manner in which the network nodes interface to the physical transmission media, (c) the process for transferring data over the physical media, and (d) the protocol of the data stream.
IEEE Standard 802.3, Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, is one of the most widely used standards for the physical layer. Commonly referred to as Ethernet, IEEE Standard 802.3 deals with transferring data over twisted-pair cables or co-axial cables which are typically more expensive than twisted-pair cables. The 10Base-T protocol of IEEE Standard 802.3 prescribes a rate of 10 megabits/second ("Mbps") for transferring data over twisted-pair cables.
Referring to the drawings, FIG. 1 illustrates how a prior art system 10 with a workstation, personal computer, file server, data terminal equipment, or other such information processing equipment, represented by CPU 12, is connected to an ethernet 22 or other types of data communications equipment represented by the media independent interface 24. In FIG. 1, ethernet controller 14, also commonly known as a Network Interface Controller, is situated between the CPU 12 and the incoming (and outgoing) ethernet 22 lines. Typically, the ethernet 22 connection consists of two pairs of twisted-pair copper cables, an incoming pair referred to as 10R and an outgoing pair referred to as 10T.
The ethernet controller 14 is responsible for controlling the transmission of outgoing data to the outgoing pair or cable and the reception of incoming data from the incoming pair or cable. For example, before being furnished to the outgoing pair or cable, the outgoing data is Manchester encoded to reduce electromagnetic interference. The Manchester encoding causes some portions of the data stream to be pulses at 10 MHz while other portions of the data stream are pulses at 5 MHz.
The ever growing need to transfer more information faster, accompanied by increases in data processing capability, is necessitating an expansion to data transfer rates considerably higher than the 10 Mbps rate prescribed by the 10Base-T protocol. As a consequence there is a 100Base-TX protocol which extends IEEE Standard 802.3 to accommodate data moving at an effective transfer rate of 100 Mbps through twisted-pair cables of presently existing systems. There are situations in which it is desirable that the physical transmission media be capable of handling data transferred through twisted-pair cables at both the 100Base-TX rate and the lower 10Base-T rate. Presently there is a need to support a PCI speed of 33 MHz on the internal PCI bus and a need to support an ethernet speed of 25 MHz maximum for the 100 MBits per second operation in order to support the full duplex mode of operation with an interpacket gap of 0.96 microseconds.
In addition to the problems associated with the transmission of data at different rates over the ethernet or the media independent interface, there are the problems associated with the varying data handling capabilities of the personal computers, workstations, file servers, repeaters, data terminal equipment, and other such information processing equipment. For example, in a personal computer system there may be other equipment or duties that the CPU 12 must attend to in addition to the receipt or transmission of data over the ethernet 22.
The ethernet controller 14 is responsible for controlling the transmission of data from the CPU 12 to the ethernet 22. One of the major problems confronted by the ethernet controller 14 is that the different memory devices in the various components are of differing sizes. For example, there is a requirement to keep semiconductor devices as small as possible. For that reason, it is advantageous to have bus sizes as small as possible without degrading performance of the device. As can be appreciated, a 16 bit bus is half the size of a 32 bit bus and if it is possible to provide the same performance with a 16 bit bus as a 32 bit bus it is preferable to design the part with a 16 bit bus. In addition, the smaller the bus size the less probability there will be manufacturing defects in the bus.
Referring to FIG. 2 the differing size components are illustrated. The SRAM 16 is a 16 bit memory device, data bus 20 is a 16 bit data bus, and the PCI BUS 18 is typically a 32 bit bus. There are presently 64 bit PCI Buses and future computer systems may all have the 64 bit PCI Bus as a standard bus size. The SRAM 16 is used as a buffer by ethernet controller 14 to prevent delays from occurring in the transmission of data either from the ethernet 22 to the CPU 12 or from the CPU 12 to the ethernet 22. Such delays could be caused, for example, by high latency in the CPU 12 or by a collision on the ethernet 22 causing a sending station to have to retransmit information that has just been sent. The various FIFOS, BX FIFO 26, MX FIFO 28, BR FIFO 30, and MR FIFO 32 are responsible for controlling the transmission of data between the various components. For example, BX FIFO 26 is responsible for receiving data from CPU 12 via PCI BUS 18, changing the format from 32 bits to 16 bits so that it can be transmitted over the 16 bit data bus 20 to SRAM 16. In addition, there is a requirement for addresses to be generated by BX FIFO 26 and MR FIFO 32 so that the information can be placed into SRAM 16 and retrieved efficiently by MX FIFO 28 and BR FIFO 30 respectively, which are responsible for changing the format from 16 bits as received from SRAM 16 into a 32 bit format.
In addition, because there is the possibility that there will be a need to receive data at the same time that there will be need to send data via ethernet 22 and also that there will be a need for the ethernet controller 14 to receive data from CPU 12 at the same time that there will be a need to send data to the CPU 12 there is a necessity for ethernet controller 14 to make intelligent choices for which data will be sent or received first and in what sequence subsequent data will be sent or received.
Because the data from the CPU 12 is being sent to the ethernet 22 there is a requirement to maintain and update the status of the data that is being sent. There are error codes and conditions that indicate whether the data has been successfully sent, has been garbled, has not been successfully sent, etc.
What is needed is an efficient and effective data structure that can be "piggy backed" to the packet for the maintenance and updating of the status of the packet.